1. Field of the Invention
The present invention relates to a DLL (Delay Locked Loop) circuit and a control method thereof, and, more particularly relates to a technique of controlling a lock time in a DLL circuit.
2. Description of Related Art
A DLL circuit compares phases between a received clock signal CLKi (reference clock) and a signal obtained by feeding back a clock signal CLKo output by a variable delay circuit (such as a voltage-controlled delay line) using a phase comparing circuit (PD), and reflects a comparison result on a delay time of the variable delay circuit. The DLL circuit performs control to advance or delay the phase of the clock signal CLKo, and finally operates such that the phases between the clock signal CLKo and the clock signal CLKi match (lock) each other.
In a conventional DLL circuit, a delay pitch of the variable delay circuit is constant. Thus, a lock time of the DLL circuit is calculated as: (“initial phase difference”/“phase adjusting step”)×“cycle time period”. Accordingly, when there is a large initial phase difference such as a time of power-input or returning to an operation mode from a standby mode, it takes a time to lock.
To shorten the lock time, Japanese Patent Application Laid-open No. H11-273342 discloses a DLL circuit that sets a delay amount to a vicinity of a delay amount required to lock on a variable delay circuit and the like, even when it is not in a normal operation mode, by measuring a delay amount corresponding to a predetermined cycles of an external clock signal by a clock-cycle measuring unit.
The following analysis is give to the present invention.
In the DLL circuit in Japanese Patent Application Laid-open No. H11-273342, it is required to include the clock-cycle measuring unit that measures a delay amount and to set the delay amount required to lock on a variable delay circuit or the like to the measured delay amount. Accordingly, operations therefore are complicated, and there is a possibility that its circuit size increases.